In the fabrication of semiconductor integrated circuit (IC) chips, it is frequently necessary to electrically isolate different devices from the semiconductor substrate and from each other. One method of providing lateral isolation among devices is the well-known Local Oxidation Of Silicon (LOCOS) process, wherein the surface of the chip is masked with a relatively hard material such as silicon nitride and a thick oxide layer is grown thermally in an opening in the mask. Another way is to etch a trench in the silicon and then fill the trench with a dielectric material such as silicon oxide, also known as trench isolation. While both LOCOS and trench isolation can prevent unwanted surface conduction between devices, they do not facilitate complete electrical isolation.
Complete electrical isolation is necessary to integrate certain types of transistors including bipolar junction transistors and various metal-oxide-semiconductor (MOS) transistors including power DMOS transistors. Complete isolation is also needed to allow CMOS control circuitry to float to potentials well above the substrate potential during operation. Complete isolation is especially important in the fabrication of analog, power, and mixed signal integrated circuits.
Although conventional CMOS wafer fabrication offers high density transistor integration, it does not facilitate compete electrical isolation of its fabricated devices. In particular, the NMOS transistor contained in a conventional CMOS transistor pair fabricated in a P-type substrate has its P-well “body” or “back-gate” shorted to the substrate and therefore cannot float above ground. This restriction is substantial, preventing the use of the NMOS as a high-side switch, an analog pass transistor, or as a bidirectional switch. It also makes current sensing more difficult and often precludes the use of integral source-body shorts needed to make the NMOS more avalanche rugged. Moreover since the P-type substrate in a conventional CMOS is normally biased to the most negative on-chip potential (defined as “ground”), every NMOS is necessarily subjected to unwanted substrate noise.
Complete electrical isolation of integrated devices has typically been achieved using triple diffusions, epitaxial junction isolation, or dielectric isolation. The most common form of complete electrical isolation is junction isolation. While not as ideal as dielectric isolation, where oxide surrounds each device or circuit, junction isolation has historically offered the best compromise between manufacturing cost and isolation performance.
With conventional junction isolation, electrically isolating a CMOS requires a complex structure comprising the growth of an N-type epitaxial layer atop a P-type substrate surrounded by an annular ring of deep P-type isolation electrically connecting to the P-type substrate to form a completely isolated N-type epitaxial island having P-type material below and on all sides. Growth of epitaxial layers is slow and time consuming, representing the single most expensive step in semiconductor wafer fabrication. The isolation diffusion is also expensive, performed using high temperature diffusion for extended durations (up to 18 hours). To be able to suppress parasitic devices, a heavily-doped N-type buried layer (NBL) must also be masked and selectively introduced prior to epitaxial growth.
To minimize up-diffusion during epitaxial growth and isolation diffusion, a slow diffuser such as arsenic (As) or antimony (Sb) is chosen to form the N-type buried layer (NBL). Prior to epitaxial growth however, this NBL layer must be diffused sufficiently deep to reduce its surface concentration, or otherwise the concentration control of the epitaxial growth will be adversely impacted. Because the NBL is comprised of a slow diffuser, this pre-epitaxy diffusion process can take more than ten hours. Only after isolation is complete, can conventional CMOS fabrication commence, adding considerable time and complexity to the manufacturing of junction isolated processes compared to conventional CMOS processes.
Junction isolation fabrication methods rely on high temperature processing to form deep diffused junctions and to grow the epitaxial layer. These high temperature processes are expensive and difficult to perform, and they are incompatible with large diameter wafer manufacturing, exhibiting substantial variation in device electrical performance and preventing high transistor integration densities. Another disadvantage of junction isolation is the area wasted by the isolation structures and otherwise not available for fabricating active transistors or circuitry. As a further complication, with junction isolation, the design rules (and the amount of wasted area) depend on the maximum voltage of the isolated devices. Obviously, conventional epitaxial junction isolation, despite its electrical benefits, is too area wasteful to remain a viable technology option for mixed signal and power integrated circuits.
An alternative method for isolating integrated circuit devices is disclosed in U.S. Pat. No. 6,855,985, which is incorporated herein by reference. The modular process disclosed therein for, integrating fully-isolated CMOS, bipolar and DMOS (BCD) transistors can be achieved without the need for high temperature diffusions or epitaxy. This modular BCD process uses high-energy (MeV) ion implantation through contoured oxides to produce self-forming isolation structures with virtually no high temperature processing required. This low-thermal budget process benefits from “as-implanted” dopant profiles that undergo little or no dopant redistribution since no high temperature processes are employed.
Dopants, implanted through a LOCOS field oxide, form conformal isolation structures that in turn are used to enclose and isolate multi-voltage CMOS, bipolar transistors and other devices from the common P-type substrate. The same process is able to integrated bipolar transistors, and a variety of double junction DMOS power devices, all tailored using conformal and chained ion implantations of differing dose and energy.
While this “epi-less” low thermal budget technique has many advantages over non-isolated and epitaxial junction isolation processes, in some cases its reliance on LOCOS may impose certain limitations on its ability to scale to smaller dimensions and higher transistor densities. The principle of conformal ion implantation in the LOCOS based modular BCD process is that by implanting through a thicker oxide layer dopant atoms will be located closer to the silicon surface and by implanting through a thinner oxide layer, the implanted atoms will be located deeper in the silicon, away from the surface.
As described, a fully-isolated BCD process with implants contoured to LOCOS, while easily implemented using a 0.35 micron based technology, may encounter problems when scaled to smaller dimensions and tighter line widths. To improve CMOS transistor integration density, it may be preferable to reduce the bird's beak taper of the field oxide layer to a more vertical structure so that the devices can placed more closely for higher packing densities. The narrow LOCOS bird's beak however may cause the width of the isolation sidewall to become narrowed and isolation quality may be sacrificed.
In situations where these problems are significant, it would be desirable to have a new strategy for fully isolating integrated circuit devices, particularly high-voltage devices, that uses a low-thermal-budget, epi-less integrated circuit process, but one that eliminates the narrow sidewall problem described above to allow more compact isolation structures.